Our design expertise covers areas like SONET, SPI-3, DS3 and ATM networking technologies and ASIC designs using HDL (VHDL/Verilog) modeling, imulation, verification and synthesis. We provide services on either or all of the following; 

  • Design : System partitioning, functional level and system level in Silicon. HDL coding.
  • Synthesis: Targeting an existing design for a specific standard cell library/FPGA. Optimization on both gate count as well as timing.
  • Verification
    Functional/Timing verification and/or validation of designs.