We verify ASIC/FPGA cores both at the functional level and timing level. The verification is done both at the top level as well as at the macro level. All the features are tested and well documented. The features are –

  • System Verilog and UVM – Universal Verification Methodology and UVM Framework provided by Mentor Graphics.
  • Verification of the design with respect to the functional specification.
  • Automated test cases generation and regression testing.
  • Complete test plan/test case documentation.